This invention concerns solid state imagers, and in particular is directed to an improved configuration of the pixels within a given column of a solid state imager. The invention is more particularly concerned with a pixel configuration that reduces the number of FETs associated with each given pixel so as to maximize the area available for collection of light.
Solid state image sensors are used in a wide variety of applications, and there has been much interest in pursuing low-cost, high-resolution, high-reliability image sensors for such applications. CMOS technology is well suited for imagers that are intended for portable applications, because of their need for a only a single power supply voltage, their ruggedness, and their inherent low power consumption. There has been great interest in achieving extremely high resolution also, which requires increased pixel density.
In imaging systems, there is a great desire for each pixel to have low noise, a high fill factor, and the smallest possible number of transistors per pixel, while maintaining quality and maximizing yield, i.e., imager chips per wafer. Pixels having only one transistor per pixel have been available only in passive imager designs, which have an inherent high noise threshold. Passive pixel designs are pixels that do not buffer the photon-generated charge during read out, with the result that there is either high noise, such as with photodiodes and charge-injection devices (CIDs) or else the information is destroyed during read out, as in charge-coupled devices (CCDs). The single FET per pixel is thus used only for addressing during reading, and not for buffering.
Imager designs that employ pixels that buffer their signal prior to read out are known, such as active pixel sensors (APSs) and active column sensors (ACSs). These designs typically have three FETs per pixel, and achieve a much lower thermal noise than seen in passive pixel designs. However, because much of the available surface area of each pixel is occupied by these transistors, and by various power and control wires that have to cross the pixels, there is less area available for the active photosensor elements.
The ideal imager will have its pixels designed to have low noise, a high fill factor, require few or no transistors, a 100% manufacturing yield, and close to zero unit cost.
Active pixel sensors, or APS sensors suffer from fixed-pattern noise or FPN and typically require three or more transistors per pixel. Numerous APS designs have added many extra FETs to overcome FPN, with some designs having as many as thirty-seven FETs per pixel (S. Kleinfleder, S. Lim, X. Liw and A. El Gamal, “A 10000 Frames/S CMOS Digital Pixel Sensor,” IEEE Journal of Solid State Circuits, Vol. 36, No. 12, December 2001). However, adding more transistors to each pixel reduces the fill factor and increases the unit cost for the imager.
ACS imagers enjoy very low fixed pattern noise, but still require at least two FETs, and normally three to four FETs per pixel, and reducing the number of FET's below this requirement will increase manufacturing yield as well as improve fill factor. An active column sensor (ACS) architecture has recently been developed, as disclosed in Pace et al. U.S. Pat. No. 6,084,229, which permits a CMOS image sensor to be constructed as a single-chip video camera with a performance equal to or better than that which may be achieved by CCD or CID imagers.
As mentioned above, APS and ACS sensors have three to four FETs for each pixel. As APS sensors suffer from FPN, many designs have added extra FETs to minimize this source of noise and distortion. Also pixel complexity has increased in many designs in order to provide additional pixel functions, such as shuttering capabilities for exposure control. However, even with only three FETs per pixel, a 1.3 mega-pixel imager will require 3.9 million transistors for the pixel array alone. The three transistor limit how small each pixel can be for a given set of process rules. Once most of the pixel area has been consumed by transistors, there is little room left to collect light, and so the conventional approach is to add micro-lenses to the imager to increase the fill factor optically. While micro-lenses permit smaller pixel size for a given set of process rules, the micro-lenses add cost to the wafer processing, and require yet another process step that can generate defects and reduce wafer yield. Therefore, the micro-lens approach is less attractive than an alternative that would increase the area of each pixel that is available for collecting light. Also, using fewer transistors per pixel would permit a number of design options, such as maintaining the pixel size and avoiding the need for micro-lenses, or increasing the pixel density by making the pixel size smaller and adding micro-lenses, or else following older and lower cost design rules for the same size pixel and also adding micro-lenses.
In order to obtain the lowest cost for a solid-state sensor, where cost is based on size or total area, it has been a goal to produce an imager which achieves the smallest size possible for an equivalent number of pixels. Typically, this would require reducing pixel size or size of the photosensitive areas down to the design limits of the process. This is especially important if the same chip has to devote a significant amount of area for its various output multiplexers and output amplifiers. Ideally, size reduction should be achieved, not by reducing the pixel photosensitive areas, but rather by reducing the area consumed by the other circuitry which is located within the pixels.
By combining the ACS technology of U.S. Pat. No. 6,084,229 and an improved pixel structure of U.S. Pat. No. 6,232,589, that is, a so-called Charge Snare Device or CSD, a pixel can designed that needs only two FETs per pixel. One of the two FETs is a sense FET, or pixel output transistor, that forms a part of the pixel column amplifier, and the other FET is a reset FET, which is needed to reset the sense node at the gate of the sense FET. In the CSD pixel arrangement, two of the usual FETs found in the prior photo-gate design, namely, the transfer FET and the select FET, are eliminated.
In the CSD-based imager of U.S. Pat. No. 6,232,589, the pixels operate without a separate selection gate. First the sense node, i.e., the input to the pixel output amplifier FET, is set to ground by gating the reset FET (which is an N-FET), so that the sense node FET is biased off and therefore isolated from the rest of the shared FETs in the same column. Thereafter, addressing of the sense FET is carried out by resetting the sense node FET from ground to 2.5 volts (for a 3.3 volt process). The photon-generated charge is collected by the photogate when a bias is applied and the active region of the silicon has been depleted. After the desired integration time, the sense node FET is selected by setting it to 2.5 volts, as just discussed. The collected photon-generated charge is transferred to the sense node when the bias applied to the photogate is removed, e.g., to 0.0 volts. The sense node, which is tied to the gate of the sense FET, physically surrounds the photogate, either completely or nearly so. The sense node connects with the gate of the sense node FET and the drain of the reset FET, as well as the sense gate of the CSD. The collected photon generated charge drifts and diffuses to the sense node. The sense node captures all or nearly all the collected charge at the photogate, as the photon-generated charge is surrounded or “snared.” This technique of sensing photon-generated charge has very low noise, as the thermal noise on the sense node can be removed by first sampling the sense node just after reset to measure background that contains such noise, and then remeasuring the sense node after the photon-generated charge has been transferred, and taking the difference between these two measurements as a pixel output. The thermal noise that is generated is correlated and subtracted, that is, the device carries out true correlated double sampling or CDS.
It would be desirable to use the same general concepts to create an imager in which the pixels had only a single FET associated with the photogate thereof, and which had the advantages of low noise and true CDS, but a single-FET design has eluded those working in this art.